1. Field of the Invention
The present invention relates to a semiconductor device having a multilayered structure of silicon and, more particularly, to a semiconductor device using an undoped polysilicon layer as a load resistor device. The present invention also relates to a static random access memory (SRAM) having the above characteristic features as a practical application of the semiconductor device.
2. Description of the Related Art
Polysilicon layers are used in various semiconductor devices as electrodes, interconnections, wirings, and load resistors. Normally used is a low resistance polysilicon layer to which a predetermined conductivity is imparted by being doped with impurities. An undoped polysilicon layer is used, however, in a high resistor device, such as a load resistor of an SRAM, a device that requires a very high resistance of giga-ohms to tera-ohms.
A multilayered structure of silicon is employed in the method of forming, in a device, a wiring layer of a low resistance and a load resistor of a high resistance. In this case, an undoped polysilicon layer and a low resistor polysilicon layer are normally used as the uppermost layer and an underlayer, respectively. FIG. 1 shows an example of such a multilayered polysilicon structure.
Reference numeral 11 in FIG. 1 denotes a p-type silicon substrate. On the surface of the silicon substrate 11, a thick field oxide 12 is selectively formed. An n.sup.+ -type source region 13 and an n.sup.+ -type drain region 14, which are isolated from each other, are formed in an active region surrounded by the field oxide 12. Above the channel region thus formed, a gate electrode 16 of the first polysilicon layer doped with phosphorus is formed, being stacked on and above a gate oxide film 15. A polysilicon wiring layer 17 is formed over apart of the field oxide 12 which adjoins the drain region 14 by patterning the first polysilicon layer. On the gate electrode 16 and the polysilicon wiring layer 17, an insulating interlayer 18 of CVD-SiO.sub.2 is formed to cover the entire surface of the silicon substrate 11 together with the gate electrode 16 and the polysilicon wiring layer 17. A resistor having a high resistance 19 is formed by linearly patterning the undoped second polysilicon layer. This resistor 19 is connected to the polysilicon wiring layer 17 via a contact hole. Above the resistor 19, aluminum (Al) wiring layers 21 and 22 are formed, being stacked on and above a CVD-SiO.sub.2 insulating interlayer 20 deposited on the entire surface of the resistor 19. Of these wiring layers, the Al wiring layer 21 is connected to the source region 13 via a contact hole. The Al wiring layer 22 is connected to the resistor 19 via a contact hole. A barrier metal layer 23 consisting of titanium nitride is interposed between the Al wiring layer 22 and the high resistor device 19.
The integration degree can be increased because, as described above, the resistor 19 can be stacked on another device in the semiconductor integrated circuit having the multilayered polysilicon structure including the undoped polysilicon layer. Note that the above example uses a two-layered polysilicon structure, and that examples using multilayered polysilicon structures of three or more layers are also well known.
In the above multilayered polysilicon structure, however, a plurality of polysilicon layers are stacked via the insulating interlayers. Therefore, patterned polysilicon layers such as the polysilicon wiring layer 17 and the resistor 19 cross complicatedly. For this reason, a cross portion where the polysilicon patterns of different layers cross each other has a large stepped portion. As a result, poor step coverage of a metal wiring layer formed on the cross portion and a short circuit or bridging occur.
A special mask is needed to pattern the polysilicon layer and form the high resistor device 19, resulting in an increase in manufacturing cost.